Please use this identifier to cite or link to this item: http://dspace.univ-bouira.dz:8080/jspui/handle/123456789/9428
Title: A probabilistic and timed verification approach of SysML state machine diagram
Authors: Bennouar, Djamal
Issue Date: 28-Apr-2015
Publisher: Université Akli Mouhand Oulhadj-Bouira
URI: http://dspace.univ-bouira.dz:8080/jspui/handle/123456789/9428
Appears in Collections:Articles

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